Matsuno Hiroshi
Affiliate Master
Yamaguchi University
Incorporation of cycles and inhibitory arcs into the timed petri net model of signaling pathway
IEICE transactions on fundamentals of electronics, communications and computer sciences Volume E96-A Issue 2
Page 514-524
published_at 2013-02
Title
Incorporation of cycles and inhibitory arcs into the timed petri net model of signaling pathway
Creator Keywords
signaling pathway
timed Petri net
retention-free Petri net
self-loop
cycle
inhibitory arc
Languages
eng
Resource Type
journal article
Publishers
電子情報通信学会
Date Issued
2013-02
Rights
copyright(c)2013IEICE()
File Version
Not Applicable (or Unknown)
Access Rights
metadata only access
Relations
[ISSN]0916-8508
[NCID]AA10826239
[NCID]AA11510296
[isVersionOf]
[URI]https://www.jstage.jst.go.jp/browse/transfun
[isVersionOf]
[URI]https://search.ieice.org/